一颗先进芯片里，80% 的面积不是"自己设计的"——硅知识产权如何撑起整座芯片产业

// minimal_soc_top.v — 极简 SoC 顶层，展示 IP 实例化
// 假设所有 IP 以软 IP (RTL) 形式交付

module minimal_soc_top (
    input  wire        clk_50mhz,
    input  wire        rst_n,
    // UART 外部引脚
    input  wire        uart_rx,
    output wire        uart_tx,
    // GPIO（定制逻辑部分）
    inout  wire [7:0]  gpio_pins
);

    // ============================================================
    // 1. IP 实例化 — 这些模块来自不同 IP 供应商，不是自己写的
    // ============================================================

    // CPU IP: ARM Cortex-M0 (软 IP，RTL 交付)
    wire [31:0] cm0_haddr;
    wire [1:0]  cm0_htrans;
    wire        cm0_hwrite;
    wire [31:0] cm0_hwdata;
    wire [31:0] cm0_hrdata;
    wire        cm0_hready;
    wire        cm0_hresp;

    cortexm0_ip u_cpu (
        .HCLK      (clk_50mhz),
        .HRESETn   (rst_n),
        .HADDR     (cm0_haddr),
        .HTRANS    (cm0_htrans),
        .HWRITE    (cm0_hwrite),
        .HWDATA    (cm0_hwdata),
        .HRDATA    (cm0_hrdata),
        .HREADY    (cm0_hready),
        .HRESP     (cm0_hresp)
    );

    // SRAM Controller IP (硬 IP 或软 IP，此处以软 IP 为例)
    wire [31:0] sram_hrdata;
    wire        sram_hready;

    sram_ctrl_ip u_sram_ctrl (
        .HCLK      (clk_50mhz),
        .HRESETn   (rst_n),
        .HADDR     (cm0_haddr),
        .HTRANS    (cm0_htrans),
        .HWRITE    (cm0_hwrite),
        .HWDATA    (cm0_hwdata),
        .HRDATA    (sram_hrdata),
        .HREADY    (sram_hready),
        .HRESP     (1'b0)  // SRAM 总是 OK
    );

    // UART IP (软 IP)
    wire [31:0] uart_hrdata;
    wire        uart_hready;

    uart_ip u_uart (
        .HCLK      (clk_50mhz),
        .HRESETn   (rst_n),
        .HADDR     (cm0_haddr),
        .HTRANS    (cm0_htrans),
        .HWRITE    (cm0_hwrite),
        .HWDATA    (cm0_hwdata),
        .HRDATA    (uart_hrdata),
        .HREADY    (uart_hready),
        .HRESP     (1'b0),
        .rx        (uart_rx),
        .tx        (uart_tx)
    );

    // ============================================================
    // 2. 总线仲裁 — 地址解码决定 CPU 访问哪个 IP
    // ============================================================

    // 地址映射 (简化):
    //   0x0000_0000 - 0x0000_FFFF: SRAM
    //   0x4000_0000 - 0x4000_FFFF: UART
    //   0x4001_0000 - 0x4001_FFFF: GPIO (定制逻辑)

    wire sram_sel = (cm0_haddr[31:16] == 16'h0000);
    wire uart_sel = (cm0_haddr[31:16] == 16'h4000);
    wire gpio_sel = (cm0_haddr[31:16] == 16'h4001);

    // 多路选择读数据
    assign cm0_hrdata = sram_sel ? sram_hrdata :
                        uart_sel ? uart_hrdata :
                        gpio_sel ? gpio_hrdata : 32'h0;

    assign cm0_hready = sram_sel ? sram_hready :
                        uart_sel ? uart_hready :
                        gpio_sel ? 1'b1 : 1'b0;

    // ============================================================
    // 3. 定制逻辑 — 这才是终端公司自己写的那 ~20%
    // ============================================================

    wire [31:0] gpio_hrdata;

    custom_gpio u_gpio (
        .clk        (clk_50mhz),
        .rst_n      (rst_n),
        .cpu_addr   (cm0_haddr[3:0]),
        .cpu_wdata  (cm0_hwdata),
        .cpu_we     (cm0_hwrite & gpio_sel),
        .cpu_rdata  (gpio_hrdata),
        .pins       (gpio_pins)
    );

endmodule